Wafer Preparation Parameter Optimization for Wafer Defects Elimination
B. C. Bacquian *
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna 4027, Philippines.
F. R. Gomez
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna 4027, Philippines.
*Author to whom correspondence should be addressed.
Abstract
In every new technology developed and introduced to the manufacturing floor, particularly in the wafer preparation, entails problems that later induce defects affecting the wafer yield. This paper discusses the optimization of wafer preparation parameters, particularly the tensionless backgrinding tape lamination and DAF cut vacuum control, that mitigates wafer yield detractors such as edge cut, kerf shift and dice pop-out. Based on the evaluation results, tensionless backgrinding lamination affects the kerf shifting and edge cutting, and with proper vacuum control to attain zero dice pop-out process.
Keywords: Wafer preparation, dicing before grinding, DAF, laser DAF cut, kerf shift.