Improvement on Semiconductor Substrate Design with Package Modeling and Simulation for Mitigation of Delamination and Voids

Frederick Ray I. Gomez *

STMicroelectronics, Inc., Calamba City, Laguna, 4027, Philippines.

Rammil A. Seguido

STMicroelectronics, Inc., Calamba City, Laguna, 4027, Philippines.

*Author to whom correspondence should be addressed.


Abstract

This technical paper presents the challenges encountered in the development of a compact and thinner package that incorporates multiple or stacked dice in one. For the case of this paper, Die1 (bottom die) is smaller than Die2 (top die) and must be the first one to be die-bonded, making the internal construction an unbalanced stacked dice. Typically, stacked dice are in pyramid layout, wherein a single large bottom die supports smaller top die. Nonetheless, success is measured when there is a solution to control or mitigate die-attach voids and eliminate or significantly minimise delamination for unbalanced stacked dice as mentioned. Ultimately, the paper presents the understanding of the factors involved and the package design optimisation approach used to produce a successful unbalanced stacked die in a thin package using a thin substrate.

Keywords: Substrate design, planarized, delamination, DAF voids, modeling, simulation


How to Cite

Gomez, Frederick Ray I., and Rammil A. Seguido. 2018. “Improvement on Semiconductor Substrate Design With Package Modeling and Simulation for Mitigation of Delamination and Voids”. Journal of Engineering Research and Reports 2 (4):1-9. https://doi.org/10.9734/jerr/2018/v2i416712.

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