Addressing Package Voids on Extremely Small Leadframe Device
A. Sumagpang Jr.
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna, 4027, Philippines.
F. R. Gomez
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna, 4027, Philippines.
*Author to whom correspondence should be addressed.
Abstract
The paper focused in addressing the package voids defect of a semiconductor device utilizing an extremely small leadframe technology. Potential risk analysis and pareto diagram were completed to identify the top reject contributors and eventually come-up with the robust solution. A comprehensive design of experiments (DOE) was completed and solution validation was performed to formulate the effective corrective actions. Results revealed that package voids were addressed by optimizing the molding process focusing on the molding temperature and curing time. A significant improvement of 95 % for package voids reduction was achieved. For future works, the parameters and learnings could be used on devices with similar configuration.
Keywords: Compression molding, leadframe, line-stressing, package voids, semiconductor