Die Placement Advancement for Prevention of Silhouetted Die Occurrence on LGA Package
Rennier Rodriguez *
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna, Philippines.
Frederick Ray Gomez
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna, Philippines.
Edwin Graycochea Jr.
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna, Philippines.
*Author to whom correspondence should be addressed.
Abstract
In semiconductor packaging industry, silhouetted die defect is occasionally encountered in singulation process esp. on substrate land grid array (LGA) package with tight clearances. This paper is focused on the prevention of the silhouetted die occurrence as it would affect the assembly yield performance of the device. The silhouetted die is caused by the tight clearance of die edge to package edge, given the machine and process tolerances. Process enhancement and optimization were done through adjusting the die placement accordingly as per the defined measurement. Eventually, the occurrence of silhouetted die was successfully mitigated by formulating the appropriate die placement references.
Keywords: BLT, die placement, LGA, silhouette.