Journal of Engineering Research and Reports https://www.journaljerr.com/index.php/JERR <p style="text-align: justify;"><strong>Journal of Engineering Research and Reports</strong>&nbsp;<strong>(ISSN: 2582-2926)</strong> aims to publish high-quality papers in all areas&nbsp;of engineering.&nbsp;The journal also encourages the submission of useful reports of negative results. This is a quality controlled,&nbsp;OPEN&nbsp;peer-reviewed, open access INTERNATIONAL journal.</p> en-US contact@journaljerr.com (Journal of Engineering Research and Reports) contact@journaljerr.com (Journal of Engineering Research and Reports) Sat, 20 Feb 2021 06:53:07 +0000 OJS 3.1.1.4 http://blogs.law.harvard.edu/tech/rss 60 Augmented Leadframe Design for Stable Multi-Wire Ground Bonding https://www.journaljerr.com/index.php/JERR/article/view/17273 <p class="Body" style="margin-bottom: .0001pt;"><span style="font-family: 'Arial','sans-serif';">Technological change has brought the global market into broad industrialization and modernization. One major application in the semiconductor industry demands safety and high reliability with strict compliance requirement. This technical paper focuses on the package design solution of quad-flat no leads (QFN) to mitigate the leadframe bouncing and its consequent effect of lifted wire and/or non-stick on leads (NSOL) defects on multi-wire ground connection. Multi-wire on single lead ground (or simply Gnd) connection plays critical attribute in the test coverage risk assessment. Cases of missing wire and/or NSOL on the multi-wire Gnd connection cannot be detected at test resulting to Bin1 (good) instead of Bin5 (open) failure. To ease the failure modes mechanism, a new design of QFN leadframe package with lead-to-diepad bridge-type connection was conceptualized for device with extended leads and with multiple Gnd wires connection. The augmented design would provide better stability than the existing leadframe configurations during wirebonding. Ultimately, the design would help eliminate potential escapees at test of lifted Gnd wire not detected.</span></p> Frederick Ray I. Gomez, Alyssa Grace S. Gablan, Anthony R. Moreno, Nerie R. Gomez ##submission.copyrightStatement## https://www.journaljerr.com/index.php/JERR/article/view/17273 Sat, 20 Feb 2021 00:00:00 +0000 Understanding Package Crack Signatures in a Leadframe Semiconductor Package https://www.journaljerr.com/index.php/JERR/article/view/17274 <p>This paper presents the simulation approach used to understand package crack signatures of a leadframe package under different mechanical loading scenarios. Package crack is one of the common problems with semiconductor packages. A better understanding of the different crack signatures would help identify the root cause quickly and be able to find the correct solution. In this study, a high precision materials testing system was used to apply mechanical loading to the package simulating different scenarios that could produce the crack. Based on the testing results, cracks have distinct signatures depending on how the force is applied. With the different signatures identified, this approach makes it easy to find the root cause of the crack in actual applications or assembly processes and resolve the problem faster.</p> Jefferson Talledo ##submission.copyrightStatement## https://www.journaljerr.com/index.php/JERR/article/view/17274 Sat, 20 Feb 2021 00:00:00 +0000 Glue Voids Reduction on QFN Device through Material and Process Improvement https://www.journaljerr.com/index.php/JERR/article/view/17275 <p>The paper is focused on the glue voids reduction on critical semiconductor quad-flat no-leads (QFN) device processed on a stencil printing type of die attach machine. Process optimization through material preparation improvement was done to mitigate the silver lumps of the sintering glue which is a main contributor on the voids occurrence. Eventually, the glue voids were reduced to less than the allowed 5% limit. For future works, the learnings and configuration could be used on devices with similar requirement.</p> Edwin M. Graycochea Jr., Endalicio D. Manalo, Rennier S. Rodriguez, Frederick Ray I. Gomez ##submission.copyrightStatement## https://www.journaljerr.com/index.php/JERR/article/view/17275 Thu, 25 Feb 2021 00:00:00 +0000 Mathematical Skills and the Academic Performance of Junior and Senior Electrical Engineering Students of the University of Eastern Philippines https://www.journaljerr.com/index.php/JERR/article/view/17276 <p>The study was conducted to determine the mathematical skills and the academic performance of the junior and senior electrical engineering students of the University of Eastern Philippines. Descriptive-correlational method of research was used with a total enumeration of the regular students from third year to fifth year electrical engineering students.</p> <table> <tbody> <tr> <td width="29"> <table width="100%"> <tbody> <tr> <td> <p>&nbsp;</p> </td> </tr> </tbody> </table> &nbsp;</td> </tr> </tbody> </table> <p>The findings revealed that male students dominated all the three year levels of the electrical engineering course. It was also found out that there were more regular fifth year engineering students than the third year and fourth year students. Meanwhile, the third year students got the highest average rating in the final grades of first year and second year mathematics and the lowest average rating belonged to the fifth year students. The learning style of the three-year levels was found to be visual while in terms of study habits, the third year students have very good study habit.</p> <p>It was also found out that the level of mathematical skills of the three-year levels were low, but the level of academic performance of the three-year levels were found out to be good. Multiple regression analysis was used to determine the relationship of the student profile and their mathematical skills. The results showed that the average of final grades in all first-year mathematics, and the students’ year level have significant relationship with the mathematical skills of the students.</p> <p>Meanwhile, the profile variables found to be significantly related to academic performance were the average of final grades in first year mathematics, average of final grades in second year mathematics and study habits of the students’ respondents.</p> <p>Lastly, the mathematical skills had no significant relationship to the academic performance of the student-respondents.</p> Kenneth Bryan F. Abaigar, Benjamin D. Varela ##submission.copyrightStatement## https://www.journaljerr.com/index.php/JERR/article/view/17276 Thu, 25 Feb 2021 00:00:00 +0000 Die Crack Resolution through Pick-up Process Optimization for BGA Package https://www.journaljerr.com/index.php/JERR/article/view/17277 <p>With the new devices and new technologies in the semiconductor industry are getting more challenging to process because issues are unavoidable especially on thin dies. The paper is focused on the improvement done on a ball grid array (BGA) substrate package assembly to address the quantity of rejection of die crack during die picking at the die attach process station. High pick force and high needle top height found out during the pick-up process is the main root cause of die crack. Parameter optimization particularly for die picking with the combination of pick force and needle top height parameter was done to eliminate this type of issue after the die attaches process. With the die attach process improvement, a reduction of 100 percent of die crack occurrence was successfully achieved. For future works, the improvement and learnings could be used for devices with similar constraints.</p> R. Rodriguez, E. Graycochea Jr., F. R. Gomez, E. Manalo ##submission.copyrightStatement## https://www.journaljerr.com/index.php/JERR/article/view/17277 Thu, 25 Feb 2021 10:12:35 +0000 Modeling Study on the Solder Joint Reliability of a Leadframe Package under Powered Thermal Cycling https://www.journaljerr.com/index.php/JERR/article/view/17279 <p>This paper aims to present a thermo-mechanical modeling approach to predict the solder joint reliability of a leadframe-based package under powered thermal cycling (PTC) test from -40<sup>o</sup>C to 105<sup>o</sup>C. The study involves modeling the PTC condition as a standard thermal cycling with a modified temperature boundary to account for the temperature increase due to the applied power to the device package mounted on board. The temperature ramp and dwell times were maintained. Based on the finite element analysis (FEA) results and comparison with actual data, modeling a PTC as a modified thermal cycling process provides a good prediction of the solder joint life. The analysis is simpler and would be beneficial for getting quick assessments of new leadframe package designs.</p> Jefferson Talledo ##submission.copyrightStatement## https://www.journaljerr.com/index.php/JERR/article/view/17279 Fri, 26 Feb 2021 00:00:00 +0000